测试挑战增加

《半导体工程》坐下来讨论了当前和未来的测试挑战，与Dave Armstrong，在Advantest的业务开发总监;Mentor Graphics Silicon Test Solutions产品营销总监Steve Pateras;Synopsys高级产品营销经理Robert Ruiz;FormFactor总裁Mike Slessor;Optimal+的首席执行官丹·格洛特(Dan Glotter)。

SE:在我们上次的讨论中，我们谈到了测试soc。我们如何测试市场上的新一波模拟/混合信号芯片?

鲁伊斯:混合信号IP测试对设计者来说是一个挑战。我们的理念是为IP提供测试。测试随部件本身一起发布。至于soc，今天已经不仅仅是数字化了。这里还涉及到混合信号。对于每一个soc，我们都有一个解决方案。但是对于混合信号测试，它是自动化的。不仅功能完整，而且他们可以将其放入设计中。客户必须装上说明书，然后启动BIST发动机。但是，我想回到先前关于会议日程安排的发言。 You need to meet the turnaround times with shrinking market windows. That automation is needed. So test needs to be provided for those parts. For parts that are custom, there are ways to help to automate portions of that, particularly the digital portions.

接线盒:模拟和混合信号测试多年来一直具有挑战性。模拟测试可能是25到30年前的数字测试。在许多方面，它就像蛮荒的西部。这是一个更难的问题。部分原因是缺乏测试模拟的结构化方法。这在很大程度上是一个动手、手工和创造性的过程。我们不具备的基本能力之一是衡量我们做得有多好。数字测试在25年前发生了转变，当时我们提出了故障模型和故障模拟的概念。这里有一个指标来告诉你我们做得有多好。这是一种了解我们的功能模式是好是坏的方法。 And then, we moved to more structural approaches. Now, we’re trying to develop the same thing for analog, which is analog-based fault simulation. How do we standardize on describing fault effects or defect effects on analog circuits? How do we measure them in some efficient way? At Mentor, we’ve developed an analog fault simulator and worked with many customers to determine how useful or efficient that is. We are also trying to get some standardization in place. Once we have that, we can start working on making those tests more efficient. We are starting to see some progress but it’s early. Certainly, there are high-speed I/Os and PLLs. We have solutions like BIST, which can test these things quite well. But if you look at more general mixed-signal components, such as DACs, ADCs and RF, then it gets trickier.

阿姆斯特朗我同意这很大程度上是蛮荒的西部。模拟测试本质上趋向于参数化。我看到模拟技术继续向数字技术迁移。射频转比特类型是新的，使我们更加数字化。但是你仍然需要很好地控制模拟源和测量它们的东西。这里的另一个趋势是系统级测试。这在很多方面填补了边缘。人们希望更多地使用它，不幸的是，据我所知，还没有错误模型来说明系统级测试如何与其余部分相结合。每个人在发货前都完成了自己的任务。有些人在晶圆探头做这个。 The challenge is how do we assimilate the systems-level test aspects and perhaps diminish the traditional scan test, as we are covering the faults otherwise.

SE:我们在堆叠芯片或2.5D/3D时代处于什么位置?你如何测试这些芯片?

接线盒:如果你熟悉高德纳公司(Gartner)的技术采用曲线，就会发现其中有炒作因素。还有采用阶段。我们已经通过了3D的宣传部分。这是一项肯定会被采用的技术，因为有大量的数据和丰富的经验。我们肯定会看到内存堆叠，无论是2.5D插入器上的内存堆栈，甚至在某些情况下，逻辑芯片上的内存堆栈。这个测试问题很好理解。通常，我们有诸如内存BiST之类的解决方案。它甚至可以是一个宽I/ based内存，但有适当的解决方案来测试堆叠内存。当你谈到一个中间人时，我不认为有什么问题。它可以用传统方法进行测试和处理。 But when you are stacking logic die and TSVs, you see more challenges. The biggest challenge is test access. From there, it’s a question of getting die from different vendors using different methodologies. How do you get test access? Standards are critical at that point. You need standards. There is a working group called 1838. They are working on a standard way of accessing dies and TSVs in a stack. It’s going painfully slow. They have been working on it for four years. But that’s going to be a necessity unless you do everything with one vendor. This could be the case in the short term. There are other factors that come into play, as well. Again, it comes back to the divide and conquer, or hierarchical, approach. If you stack multiple die, you want to test the die individually and then test them in the stack. This means you need to re-use those tests. You don’t want to re-generate a test for the stack. And then, in the third component, wafer sort becomes much more critical. You don’t want to be stacking bad die. So, the whole known good die issue comes back into play. You need to do more and more testing at the wafer level. By that, I mean mixed-signal and I/O. Things like high-end I/O become critical at wafer sort. We are already seeing that happening in terms of pushing more things at wafer sort. That will drive more embedded test and more on-chip DFT resources. It will eliminate the constraints that may exist at wafer sort probing.

阿姆斯特朗:我确实认为人们正在取得良好的进展，有些人实际上已经在这个领域推出了产品。我们需要回到故障模型，看看这些设计会发生什么。问题会在那里传播。但对我们所有人来说，真正的挑战是找出测试插入点在哪里。晶圆上芯片是一种方法，但还有其他方法。另一个归结为装箱问题。这又回到了系统级测试。这可以让我知道我的箱子是1号，2号还是3号。我想确保我在相同的中间体上有垃圾箱，并运送该产品。我不想让三号箱子在里面，然后扔掉一号箱子的部分。 We simply can’t throw out an expensive ASIC because of a 50-cent DRAM. There are a lot of challenges here and that’s why I believe wafer probe is seeing a resurgence.

Glotter:从我们的角度来看，我们并不关心它是2.5D还是3D。一般来说，我们称之为mcp。顺便说一下，3D存在于内存中。一种叫做混合内存立方体。还有其他创新公司在开发mcp，比如Xilinx和其他公司。总之，如果没有一个叫做清算所的新概念，整个问题就不会存在。让我们以赛灵思为例。您正在从多家公司采购部件，例如内存、模拟和soc。今天，只有“好垃圾桶”的概念。但是当把它们堆在一起时，你可能会从一个公司的晶圆边缘取一个器件。 You might have another device that has been tested at one step. And then, you have a device with some issues. And if you stack them together, you may get a scrambled egg. That scrambled egg may come back as an RMA. Now, what we are doing for our customers is taking care of the databases of the RMAs. You see issues, because it’s a scrambled egg. It could be a performance issue. Or it can be a reliability issue. We are trying with our customers to create a consortium. It’s not exactly a consortium, but it’s a group that will say: ‘This is the clearinghouse. This is the clearinghouse methodology. And in this methodology, this is how one company, Toshiba, needs to speaks with Intel, Qualcomm or Broadcom.’ It’s a whole new concept on how you deal with this MCP arena.

鲁伊斯:我们已经就所有3D-IC实现与相当多的客户进行了交谈。他们正在考虑各种各样的挑战，比如热分析和路由技术。最大的挑战更多的是在设计方面。最不感兴趣的部分实际上是测试。但是还需要做测试。对于客户来说，这是最不有趣的，因为他们使用现有的技术。有板级测试技术，可应用于3D测试。像P1838这样的标准将有所帮助。这将有助于提高工作效率。但我认为真正的问题是方法和测试成本，这是3d - ic实现的最大驱动因素或担忧。 Regarding implementing test for 3D-ICs, there are well known techniques. Perhaps we can look at additional fault models for 3D-ICs.

Slessor挑战不在于怎么做。而是如何去做，如何达到成本目标。这是需要权衡的。为了更好地了解将要封装在一起的单个晶圆芯片，晶圆测试肯定会受到更大的重视。这包括晶圆测试的保真度，探针卡的清洁程度，以及要运行多少不同的向量来查找不同的故障模式。这是关键，尤其是在产品生命周期的早期，你还在学习这个模具是如何失败的，在哪里你会有yield问题。业界至少已经用多芯片模块部分解决了这个问题。但是如何分配我的预算来测试这个产品，以及在不同成本和复杂性的不同部分之间，这主要是一个经济考虑，而不是一个技术问题。它是在找出如何以某种方式解决这些问题，在某个成本点上提供最终用户想要的性能，使他们能够拥有成功的业务。这就是我们正在努力解决的问题。 How much are you going to test known good die? And how much are you going to do known good partial stacks and all of these different test insertions you can envision? You can’t do them all. Otherwise, you will lose money.

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