如何弥补另一个node’s worth of power, performance and area benefits from existing nodes.
David Fried, vice president of computational products at Lam Research, looks at shrinking tolerances at advanced processes, how that affects variation in semiconductor manufacturing, and what can be done to achieve the benefits of scaling without moving to new transistor architectures.
But gaps in tools make it difficult to address warpage, structural issues, and new materials in multi-die/multi-chiplet designs.
Technology and business issues mean it won’t replace EUV, but photonics, biotech and other markets provide plenty of room for growth.
GlobalFoundries sues IBM; EU’s $47B chips plan; China chip output falls; Space Forge opening US facility; first LPDDR flash memory; transformable nano-scale electronic devices; tabletop 3D X-ray microscopy.
Gate-all-around is set to replace finFET, but it brings its own set of challenges and unknowns.
Checks, balances, and unknowns for AI/ML in semiconductor design.
While terms often are used interchangeably, they are very different technologies with different challenges.
Less precision equals lower power, but standards are required to make this work.
Commercial chiplet marketplaces are still on the distant horizon, but companies are getting an early start with more limited partnerships.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
Existing tools can be used for RISC-V, but they may not be the most effective or efficient. What else is needed?
Open source by itself doesn’t guarantee security. It still comes down to the fundamentals of design.
How customization, complexity, and geopolitical tensions are upending the global status quo.
何行业取得了理解w aging affects reliability, but more variables make it harder to fix.
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