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Memory Evolution Drives Requirements For Design Technology Co-Optimization


By Ricardo Borges and Anand Thiruvengadam As new technology nodes have become available, memory has been one of the most aggressive semiconductor applications to adopt advanced process technology. The relentless demand by users of electronic devices for more memory has ensured that investments in new nodes and processes would be quickly repaid by massive sales volumes. As each new node came ...» read more

Why It’s So Difficult — And Costly — To Secure Chips


Rising concerns about the security of chips used in everything from cars to data centers are driving up the cost and complexity of electronic systems in a variety of ways, some obvious and others less so. Until very recently, semiconductor security was viewed more as a theoretical threat than a real one. Governments certainly worried about adversaries taking control of secure systems through...» read more

Building Complex Chips That Last Longer


Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co...» read more

What’s Changing In DRAM


Most of the attention in chip scaling has been focused on logic and on-chip memory, but off-chip memory is starting to encounter problems, as well. David Fried, vice president of computational products at Lam Research, looks at the impact of shrinking features and increasing density, including variation, thermal effects and aging, as well as effects such as micro-loading and DRAM stacking.» read more

Tradeoffs To Improve Performance, Lower Power


Generic chips are no longer acceptable in competitive markets, and the trend is growing as designs become increasingly heterogeneous and targeted to specific workloads and applications. From the edge to the cloud, including everything from vehicles, smartphones, to commercial and industrial machinery, the trend increasingly is on maximizing performance using the least amount of energy. This ...» read more

Chiplets For The Masses


Chiplets are a compelling technology, but so far they are available only to a select few players in the industry. That's changing, and the industry has taken little steps to get there, but timing for when you will be able to buy a chiplet to integrate into your system remains uncertain. While new fabrication nodes continue to be developed, scaling is coming to an end, be it for physical or e...» read more

Structural Integrity Of Chips


A new challenge is on the horizon, and it's one that could have some interesting consequences for chip design — structural integrity. Ever since the introduction of finFETs and 3D NAND, the lines have been blurring between electrical and mechanical engineering. After some initial reports of fins collapsing or breaking, and variable distances between layers, chipmakers figured out how to so...» read more

Are Chips Getting More Reliable?


The semiconductor industry is making huge progress in understanding the causes and telltale signs of circuit aging and irregular behavior. But are devices actually getting more reliable? The answer depends on a number of factors, none of which is easily measured. To be sure, circuits are much better designed and inspected than in the past, and the individual components are printed more accur...» read more

3nm: Blurring Lines Between SoCs, PCBs And Packages


尖端chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ...» read more

Where Timing And Voltage Intersect


João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing.» read more

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