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tag:OIF

1.6 Tb/s Ethernet Challenges
ByEd Sperling- 16 Nov, 2021 - Comments: 0

以超级快的速度移动数据听起来不错theory, but it raises a number of design challenges. John Swanson, senior product marketing manager for high-performance computing digital IP at Synopsys, talks about the impact of next-generation Ethernet on switches, the types of data that need to be considered, the causes of data growth, and the size and structure of data centers, both in the...» read more

Many Chiplet Challenges Ahead
ByBrian Bailey- 12 Apr, 2021 - Comments: 0

Over the past couple of months, Semiconductor Engineering has looked into several aspects of 2.5D and 3D system design, the emerging standards and steps that the industry is taking to make this more broadly adopted. This final article focuses on the potential problems and what remains to be addressed before the technology becomes sustainable to the mass market. Advanced packaging is seen as ...» read more

Waiting For Chiplet Standards
ByBrian Bailey- 25 Mar, 2021 - Comments: 2

The need and desire for chiplets is increasing, but for most companies that shift will happen slowly until proven standards are in place. Interoperability and compatibility depend on many layers and segments of the supply chain coming to agreement. Unfortunately, fragmented industry requirements may lead to a plethora of solutions. Standards always have enabled increasing specialization. ...» read more

Emerging Apps And Challenges For Packaging
ByMark LaPedus- 23 Nov, 2020 - Comments: 0

广告vanced packaging is playing a bigger role and becoming a more viable option to develop new system-level chip designs, but it also presents chipmakers with a confusing array of options and sometimes a hefty price tag. Automotive, servers, smartphones and other systems have embraced advanced packaging in one form or another. For other applications, it's overkill, and a simpler commodity pack...» read more

Designs Beyond The Reticle Limit
ByBrian Bailey- 12 Nov, 2020 - Comments: 0

Designs continue to grow in size and complexity, but today they are reaching both physical and economic challenges. These challenges are causing a reversal of the integration trend that has provided much of the performance and power gains over the past couple of decades. The industry, far from giving up, is exploring new ways to enable designs to go beyond the reticle size, which is around 8...» read more

Momentum Builds For Advanced Packaging
ByMark LaPedus- 17 Sep, 2020 - Comments: 0

The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs. Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce p...» read more

High-Speed Signaling Drill-Down
ByBryon Moyer- 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ...» read more

The Good And Bad Of Chiplets
ByMark LaPedus- 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu...» read more

Die-to-Die Interconnects for Chip Disaggregation
ByMondeep Thiara- 10 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increa...» read more

Die-To-Die Interconnects For Chip Disaggregation
ByMondeep Thiara- 09 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin...» read more

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