专家们表:SoC原型

由安Steffora Mutschler

系统级设计坐下来讨论SoC原型希勒尔米勒pre-silicon验证/飞思卡尔半导体仿真经理;弗兰克Schirrmeister、集团总监、产品营销、系统开发套件的节奏;和米克·波斯纳Synopsys对此产品营销主管。以下是摘录的谈话。

道防线:今天是如何SoC原型使用和最大的增长潜力是什么技术?

米勒:我们开始认真的虚拟样机大约五年前P4080与我们的第一代产品。我们预订了一个公司,Virtutech,他们建立了一个模型的SoC。这是一个巨大的努力。它花费很多钱。我们就是这么做的,然后我们停止做这些事情,因为成本高,然后Virtutech买下了风河,它买下了英特尔并没有使它更好。我们一直在做的是很多钯。开始的我们有这些基准性能验证。我们有一大堆的基准,我们需要运行并不是一项容易的任务,因为它涉及许多团队协调和推动。你必须把他们得到的答案,帮助你调试场景理解为什么你不满足性能目标。这是一个很有趣的活动,但需要很长时间,今天是在盖茨tapeout。 We don’t tapeout without a clear understanding of the performance. It’s used again when silicon comes back. In silicon if they can’t meet performance, you go back to the Palladium and use RTL validation and in that validation flow, we use bits and pieces of software so we have the software guys. I would say the software guys are in the beginning stages of using the emulator. For the next generation, there is a strong drive to move towards FPGA [prototyping] because the software guys really have a need to get a 10X improvement in performance. The concern about FPGAs at this point in time compared to the Palladium – the Palladium is an emulator where you work top-down. You can take an SoC, put it in the box and you can get it to work. FPGAs, especially where there’s a requirement to be 10X faster, you have to really have a disciplined design process, which is called ‘Design for FPGA,’ and you have to work bottom-up. The concern is that additional effort you’re going to put on the different design teams—and design teams do stuff only when they get something out of it. If they’re not going to get any advantage of using an FPGA and it’s going to be a software thing only, it’s going to be an issue. We are trying to figure out how to think up a bottoms-up approach with FPGAs, how to get the design teams involved, how to get them excited by [the ability to run much faster], the chance to find corner cases is much higher, better turnaround time when we’re developing our software test cases—those types of things.

Schirrmeister:没有“一刀切”引擎的原型是验证的关键驱动硬件——你需要它之前你带;然后越来越多,它的软件,真正驱动整个上下文。我们看到我们的客户使用它的方式是真的这连续的不同需求,你当你需要切换变得足够大。例如,虚拟prototyping-there需要和公司仍然做很多软件开发者他们回来,给他们一些平行的。大的例子有TI OMAP之类的东西,曾经从Virtio Synopsys对此收购的一些工具。这都是为了满足软件开发早期,但它不是hardware-accurate。如果你需要硬件验证你去RTL模拟。然后,非常准确,不错,快速周转调试。但对于软件开发人员甚至不是一杯咖啡互动。他们不会碰它。 You can force them perhaps for very low level, bare metal drivers to do something like hook up an ISS. If you need more and more software then you need to really see where your RTL stands. When customers decide, they use an emulator in cases where you really need multiple RTL drops per day, so that’s the phase where the RTL isn’t stable yet. Arguably, the software developer won’t be able to actually deal with that fast-changing RTL so you need some interface constant on the registers. But then, if the RTL isn’t fully stable yet, then the emulation flow makes sense. But as Hillel pointed out, at one point you need a 10X to really do software. That’s when FPGA-based prototyping comes in and saves the day. After optimization you’re getting up to 20, 30 or 40 megahertz. That’s where you get the classic software development. Where you pay is that you don’t have full insight into hardware anymore, so the software developer really sees it like a board, just like earlier, and it probably still takes longer to set up than emulation. But those are really the tradeoffs you make, and we see that across the board and it extends into the real chip.

波斯纳:我们一直看着高水平的用例:验证和验证。与验证你检查什么东西满足spec-perfect模拟器,适合模拟。你检查规范协议基于测试的刺激。与验证,你检查,满足用户需求,这可能是性能或图形用户界面。但是没有一个地方你说,验证已经结束,确认正在开始。模糊的线,虽然有东西会推动你在这个方向上。当你通过验证任务,最终你会做IP集成。在这一点上你要开始整合一些软件。如果你综合pci - express,以太网,USB,会有低级软件。并不是所有的硬件协议。 And those drivers you may not be developing yourself. You’re somewhat doing a validation task where you’re just testing that they run on the IP. That’s where the blurry line comes. But then when you move further into things like system validation, now you’re actually plugging in that USB connection, that Ethernet connection into something else, checking interoperability. Then you’re in the world where FPGA-based prototyping comes alive because you’re in an area that requires performance that you would love to get in an emulation environment but you can’t. All of these protocols have minimum clock frequencies typically, so you have to meet 125MHz for PCI Express. You have to meet 62.415MHz for USB3. That’s what pushes you more into the FPGA space. At the same time you’re then splitting out—you’re doing hardware/software integration, system validation and software development. And still, the FPGA-based platforms predominantly are used for software development. But again, it’s a bit of a mix. You’re still doing hardware/software verification because you’re testing the bits together. Sometimes that’s the first time where multicore may be really coming alive—physical hardware interrupts to the software.

道防线:有甜点的使用模型?

Schirrmeister:是的,有一边使用模型的技术,但是如果我看每个技术的纯甜的斑点,这是真正的软件开发。当FPGA适合在大多数和虚拟原型非常早期的。验证的硬件,这就是传统的RTL模拟进来,加速度,仿真。然后硬件今天这么复杂,至少是裸露的金属部分的软件需要在仿真和即使在RTL模拟,长大,因为它只是不做它应该做的事情没有裸金属软件。这是一个软件开发的问题。我们看到早期的虚拟部分去更高级的方面。

道防线:工程团队如何决定何时采用仿真和FPGA原型和模拟?

波斯纳:踢翻点通常是性能。如果你不能完成工作的技术,你移动到下一个技术。软件工程师,如果你问他们想要的有多快,他们想要它。最终它应该以相同的速度运行结束的筹码。你永远不会得到。

米勒:我们试着看看的一件事就像你有混合动力的汽车,你有一个电动马达和节省就想看看如何快速混合之类的虚拟ISS和钯甚至仿真的模型。我还没有真正见过这些多核芯片32核心,但是你可以实例化32快速模型。今天我们还没有成功,但我们正在尝试它。不过,你看数学和你没有看到,你会得到的增益性能。你肯定会得到盖茨的增益,但你能建立一个模型,将满足软件工程师。这是一个探索,但它将会很高兴知道,EDA行业实际上是未来混合动力解决方案的工作。

Schirrmeister:这都是关于速度。发生了什么在仿真有一定的任务,只是天生在硬件上做得很好,这是并行任务。所以对于一个图形引擎,你能抽象吗?是的,你可以抽象的api进行渲染,然后你可以重新映射到本地主机环境。但它不是真的执行你实现你的图形芯片。这些固有的并行things-video被另一个主导你最好做一个基于硬件加速仿真和FPGA。然后在前面的软件模型从手臂或任何你把快。我们看到,绝对是一个趋势。