中文 English

tag:clock gating

Power Domain Implementation Challenges Escalate
ByAnn Mutschler- 20 Jun, 2022 - Comments: 0

The number power domains is rising as chip architects build finer-grained control into chips and systems, adding significantly to the complexity of the overall design effort. Different power domains are an essential ingredient in partitioning of different functions. This approach allows different chips in a package, and different blocks in an SoC, to continue running with just enough power t...» read more

Power-Aware Test: Addressing Power Challenges In DFT And Test
ByRahul Singhal- 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si...» read more

Lower Power Chips: What To Watch Out For
ByAnn Mutschler- 08 Jul, 2021 - Comments: 0

Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos...» read more

Power Optimization: What’s Next?
ByBrian Bailey- 17 May, 2021 - Comments: 2

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing...» read more

Reducing Power At RTL
ByAnn Mutschler- 13 Feb, 2020 - Comments: 0

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on interactions with other components. This has been a growing problem in leading-edge designs for the past couple of process nodes, but similar issues have begun creeping into less-sophisticated designs as...» read more

Managing Power Dynamically
ByAnn Mutschler- 18 Dec, 2019 - Comments: 1

Design teams are beginning to consider dynamic power management techniques as a way of pushing the limits on performance and low power, leveraging approaches that were sidelined in the past because they were considered too difficult to deploy. Dynamic voltage and frequency scaling (DVFS), in particular, has resurfaced as a useful approach. Originally intended to dynamically balance performan...» read more

相互依赖的复杂电网集成电路设计
ByAnn Mutschler- 12 Dec, 2019 - Comments: 0

Creating the right power grid is a growing problem in leading-edge chips. IP and SoC providers are spending a considerable amount of time defining the architecture of logic libraries in order to enable different power grids to satisfy the needs of different market segments. The end of Dennard scaling is one of the reasons for the increased focus. With the move to smaller nodes, the amount of...» read more

Power Complexity On The Rise
ByAnn Mutschler- 14 Nov, 2019 - Comments: 0

New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s...» read more

Focus Shifts To Wasted Power
ByBrian Bailey- 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ...» read more

Optimizing Power For Learning At The Edge
ByBrian Bailey- 08 Aug, 2019 - Comments: 0

Learning on the edge is seen as one of the Holy Grails of machine learning, but today even the cloud is struggling to get computation done using reasonable amounts of power. Power is the great enabler—or limiter—of the technology, and the industry is beginning to respond. "Power is like an inverse pyramid problem," says Johannes Stahl, senior director of product marketing at Synopsys. "T...» read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2023 SMG |Terms of Service|Privacy Policy
Baidu