tag:abstraction

A New Breed Of EDA Required
ByBrian Bailey- 23 Jun, 2022 - Comments: 1

While doing research for one of my stories this month, a couple of people basically said that applying methodologies of the past to the designs of today can be problematic because there are fundamental differences in the architectures and workloads. While I completely agree, I don't think these statements go far enough. Designs of today generally have one of everything — one CPU, one accel...» read more

Missing Interposer Abstractions And Standards
ByBrian Bailey- 29 Nov, 2021 - Comments: 0

的design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab...» read more

Dealing With Market Shifts
ByBrian Bailey- 28 Oct, 2021 - Comments: 1

Back in the days when I was in EDA development, I was taken in by the words of Clayton Christensen when he published "The Innovators Dilemma." He successfully introduced the technology world to the ideas of disruptive innovation. One of the key takeaways was that you should always be working to make your own successful products redundant, or someone else will do it for you. One tool I worked...» read more

Creating Better Models For Software And Hardware Verification
ByEd Sperling- 04 Aug, 2020 - Comments: 1

半导体工程坐下来讨论's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt...» read more

A Different View On Debugging
ByHagai Arbel- 01 Jun, 2020 - Comments: 0

的classic approach to improve an engineering task that is becoming too complex due to its size and detail is to raise the abstraction of design representation. In this way we plan cities, build aircraft and plan 500M gate SoCs. For example, there is no way an ASIC design could go beyond a few thousand logic gates without shifting abstraction to the Register Transfer Level (RTL) and leveragin...» read more

为什么Is PSS So Important?
ByEd Sperling- 25 Feb, 2020 - Comments: 0

Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save.» read more

Addressing Pain Points In Chip Design
ByEd Sperling- 13 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx, Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll...» read more

Does System Design Still Need Abstraction?
ByFrank Schirrmeister- 24 Oct, 2019 - Comments: 0

About 15 years ago, the assumption in the EDA industry was that system design would be inevitable. The transition from gate-level design to a new entry point at the register transfer level (RTL) seemed complete with logic synthesis becoming well-adopted. The next step seemed to be so obvious at the time: High-level synthesis (HLS) and transaction-based development beyond RTL—also taking into ...» read more

How To Optimize Verification
ByBrian Bailey- 25 Jul, 2019 - Comments: 0

的rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many...» read more

Building An Efficient Inferencing Engine In A Car
ByEd Sperling- 05 Jun, 2019 - Comments: 0

David Fritz, who heads corporate strategic alliances at Mentor, a Siemens Business, talks about how to speed up inferencing by taking the input from sensors and quickly classifying the output, but also doing that with low power.» read more

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