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CEO Outlook: More Data, More Integration, Same Deadlines
ByEd Sperling- 24小君,2021- Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ...» read more

Versal Premium ACAPs: Breakthrough Integration of Networked IP On A Power-Optimized, Adaptable Platform
ByXilinx- 01 Dec, 2020 - Comments: 0

In every market across the world, continuous demand for higher bandwidth metro and core networks scales beyond what today's technologies can support. Data center-centric scientific, enterprise, and consumer applications demand more efficient, higher performance compute that scales beyond what traditional technologies can match. Discrete solutions cannot meet performance, thermal, and bandwidth ...» read more

Increase In Analog Problems
ByBrian Bailey- 19 Oct, 2020 - Comments: 6

Analog and mixed signal design has always been tough, but a resent survey suggests that the industry has seen significantly increased failures in the past year because the analog circuitry within an ASIC was out of tolerance. What is causing this spike in failures? Is it just a glitch in the data, or are these problems real? The answer is complicated, and to a large extent it depends heavily...» read more

Productivity Keeping Pace With Complexity
ByBrian Bailey- 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo...» read more

The Problem With Post-Silicon Debug
ByAnn Mutschler- 28 Feb, 2019 - Comments: 0

Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ...» read more

Arm Enterprise Virtualization With Arm System IP, Backplane Integration And Performance
ByArm- 03年10月,2018 -评论:0

Virtualization has become ubiquitous across the infrastructure market, increasing efficiency and security, boosting productivity and reducing operating costs. However, system performance remains crucial to ensuring a virtualized environment does not affect the end user’s experience. Performance within this environment depends on a number of factors such as transaction bandwidth, latencies an...» read more

NIWeek Test Talk
ByJeff Dorsch- 12 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down with David Hall, Chief Marketer, Semiconductor, of National Instruments, and Mike Watts, NI’s Senior Solutions Marketer, Semiconductor Test, during NIWeek 2018 in Austin, Texas. “One of the opportunities for National Instruments is that over the last 10 years, we’ve seen larger semiconductor organizations change the way they do testing both for R&...» read more

The Trouble With Models
ByEd Sperling- 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ...» read more

System Design And Verification Challenges: Are They On- Or Off-Chip?
ByFrank Schirrmeister- 28 Sep, 2017 - Comments: 0

What are the next natural items for mobile devices to be integrated? From 2002 to today, previously separate items (like GPS, cameras and keyboards) have been integrated into the phone. They caused a frenzy of integration within systems on chips. Now we have the Internet of Things (IoT) adding a trillion devices to the picture. Which ones are to be integrated, if any? What does all this mean fo...» read more

Plugging Gaps In Advanced Packaging
ByAnn Mutschler- 27 Sep, 2017 - Comments: 0

The growing difficulty of cramming more features into an SoC is driving the entire chip industry to consider new packaging options, whether that is a more complex, integrated SoC or some type of advanced packaging that includes multiple chips. Most of the work done in this area so far has been highly customized. But as advanced packaging heads into the mainstream, gaps are beginning to appea...» read more

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